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| PMC-Sierra,Inc. PM7381 FREEDM-32A672 Frame Engine and Data Link Manager FEATURES The FREEDM-32A672 chip offers the following features: * Single-chip multi-channel HDLC controller with a 50 MHz, 16-bit Any-PHY Packet Interface (APPI) for transfer of packet data using an external controller. Each APPI bus can support up to seven FREEDM-32A672 devices to enable high-density and low-latency applications. * Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 H-MVIP digital telephony buses at 2.048 Mbit/s per link, or 8 H-MVIP buses at 8.192 Mbit/s per link. * Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 channelized T1/ J1/E1 links. You can program the number of time-slots assigned to an HDLC channel from 1 to 24 (for T1/J1) and from 1 to 31 (for E1). * Supports up to 32 bi-directional HDLC channels, each assigned to an unchannelized arbitrary-rate link, subject to a maximum aggregate link clock-rate of 64 MHz in each direction. * Channels assigned to links 0 to 2 support clock rates up to 52 MHz. Channels assigned to links 3 to 31 support clock rates up to 10 MHz. In the special case, where no more than 3 high-speed links are used, the maximum aggregate link clock-rate is 156 MHz. * Links configured for channelized T1/J1/E1 or unchannelized operation support the gapped-clock method for determining time-slots, which is backwards compatible with the FREEDM-8 and FREEDM-32 devices. * For each channel, the HDLC receiver supports programmable flag-sequence detection, bit de-stuffing and frame-check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame-check sequences. * For each channel, the HDLC transmitter supports programmable flag-sequence generation, bit stuffing and frame-check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame-check sequences. The RSTB SYSCLK PMCTEST BLOCK DIAGRAM RBD RBCLK RD[31:0] RCLK[31:0] RFPB[3:0] RMVCK[3:0] RMV8DC RMV8FPC RFP8B TD[31:0] TCLK[31:0] TFPB[3:0] TMVCK[3:0] TMV8DC TMV8FPC TFP8B Receive Channel Assigner (RCAS672) Receive HDLC Processor (RHDL672) 32 k Receive Partial Packet Buffer Receive Any-PHY Packet Interface (RAPI672) Performance Monitor (PMON) Transmit Channel Assigner (TCAS672) RXCLK RXADDR[2:0] RPA RENB RXDATA[15:0] RXPRTY RSX REOP RMOD RERR RVAL Transmit HDLC Processor (THDL672) 32 k Transmit Partial Packet Buffer Transmit Any-PHY Packet Interface (TAPI672) Microprocessor Interface JTAG TXCLK TXADDR[12:0] TPA1[2:0] TPA2[2:0] TRDY TXDATA[15:0] TXPRTY TSX TEOP TMOD TERR PMC-1980428 (r2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE TRSTB TMS TCK TD1 TD0 TBD TBCLK D[15:0] A[11:2] ALE CSB WRB RDB INTB (c) 2001 PMC-Sierra, Inc. PM7381 FREEDM-32A672 Frame Engine and Data Link Manager transmitter also aborts packets under the direction of the host or automatically when the channel underflows. * Provides 32 kbytes of on-chip memory for partial packet buffering in both the transmit and receive directions. You can configure this memory to support a variety of different channel configurations: from a single channel with 32 kbytes of buffering to 672 channels, each with a minimum of 48 bytes of buffering. * Provides a standard five signal P1149.1 JTAG test-port for boundary scan board-test purposes. * Supports 5 Volt tolerant I/Os for non-APPI signals. Supports a 3.3 Volt APPI signaling environment. * 329-pin plastic ball grid-array (PBGA) package. APPLICATIONS Use the FREEDM-32A672 chip in the following applications: * Remote Access Concentrators. * Frame Relay/Multiservice Switches. * Multiservice Access Concentrators. * Internet/Edge Routers. * Packet Based DSLAM Equipment. TYPICAL APPLICATIONS EIGHT LINK T1/E1 PORT ADAPTER FOR PPP PROCESSING SBI 8 PM4318 OCTLIU Any-PHY (Packet) PM4332 TE-32 PM7380 FREEDM32A672 Packet Mamory 8 PM4318 OCTLIU 32xT1/E1/J1 8 PM4318 OCTLIU Processor 8 PM4318 OCTLIU N*DS3 FRAME RELAY TO ATM INTERWORKING Any-PHY (Packet) PM7381 FREEDM32A672 UTOPIA/ Any-PHY (Cell) Frame Relay to ATM AAL-5 SAR Interworking DS3 PM8316 TEMUX-84 APPI Interface DS3 PM8316 TEMUX-84 PM7381 FREEDM32A672 Packet Memory Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-1980428 (r2) (c) 2001PMC-Sierra, Inc. Aug.2001. FREEDM-32A672, Any-PHY, FREEDM-8, FREEDM-32, OCTLIU, TE-32, TEMUX, SBI and PMC-Sierra are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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